[7/24] SSCS DL Talk: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
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작성자 최고관리자 댓글 조회 작성일 25-07-16 11:32본문
- 강연자
- Prof. Tetsuya Iizuka, University of Tokyo
- 초청자
- 박관서 교수
제목: SSCS DL Talk: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation
연사: Prof. Tetsuya Iizuka, University of Tokyo
일시: 2025.07.24. (목) 14:00
장소: 연세대학교 제4공학관 D601
내용: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration.
초청자: 시스템반도체공학과 박관서 교수 (kwanseo@yonsei.ac.kr)
연사: Prof. Tetsuya Iizuka, University of Tokyo
일시: 2025.07.24. (목) 14:00
장소: 연세대학교 제4공학관 D601
내용: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration.
초청자: 시스템반도체공학과 박관서 교수 (kwanseo@yonsei.ac.kr)
